Three-dimensional semiconductor packages have become essential to achieve higher density and capacity. Three-dimensional packaging technology is a semiconductor fabrication technology in which semiconductor chips are thinned and further stacked and interconnected by through-silicon vias (TSVs) to form a multilayer structure. Fabrication of such packages requires the step of thinning a substrate having a semiconductor circuit formed therein by grinding its non-circuit forming surface (also referred to as “back surface”) and the step of forming TSVs and electrodes on the back surface. Prior to the step of grinding the back surface of a silicon substrate, a back surface protective tape is conventionally attached to the surface of the silicon substrate opposite to the surface to be ground to prevent the wafer from breaking during the grinding step. However, this tape uses an organic resin film as its supporting base material, and is therefore flexible but has insufficient strength and heat resistance. For this reason, this tape is not suitable for use in the TSV-forming step and the step of forming an interconnection layer on the back surface.
Therefore, a system has been proposed in which a semiconductor substrate is bonded to a support made of silicon or glass with an adhesive layer being interposed between them so that the semiconductor substrate can sufficiently withstand the step of grinding the back surface and the step of forming TSVs and electrodes on the back surface (Patent Documents 1 and 2). Such TSV-related technology is expected as the technology for high density interconnection between chips, especially the technology for connecting a high-bandwidth memory to a processor, but is now applied only to some limited applications because of high costs.
In recent years, FOWLP (Fan-Out Wafer Level Package) has received attention (Patent Document 3). This FOWLP is a package having a structure in which an insulated fine redistribution layer (RDL) is formed on an IC chip so as to be fanned out of the chip area. This package can achieve high-density wiring between a plurality of chips and have much smaller size and thickness than conventional packages.
Particularly, a technique called RDL first has been studied which involves direct processing of RDL formation on a support substrate, placement of device chips, and resin encapsulation in order to improve the accuracy of alignment of RDL with chips so that FOWLP can be applied also to an application processor having numerous terminals. The support substrate needs to be separated after RDL formation and packaging. However, this technique is different from a technique in which the back surface of a semiconductor substrate is processed after the semiconductor substrate is bonded to a support, and therefore there is a problem that the adhesive system used in the TSV forming technology cannot be applied to this technique.
Under the circumstances, a structure has recently been studied which has a release layer containing a laser-decomposable resin on a support (Patent Document 4). In this case, an RDL layer is directly formed on a release layer. However, when the release layer that remains on the RDL layer after the support is separated by laser irradiation is made of a thermoplastic resin that can be washed away with a solvent, there is a fear that the release layer deforms under high-temperature conditions for curing an insulating layer during formation of the RDL layer so that metal wirings also deform.